1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same and, more specifically, to a nonvolatile memory device with non-planar gate insulating layer and method of fabricating the same.
2. Discussion of Related Art
A non-volatile memory device can maintain stored information when power is no longer supplied to the device. As the tendency of making electronic devices smaller, e.g., pocket-sized and portable PCs, there is an increase in the demand for non-volatile memory devices. The most popular and widely used non-volatile memory device is a FLASH memory device including a floating gate.
A large potential difference of about 10V or more is used for programming and erasing the non-volatile memory of a FLASH memory device. The programming and erasing steps are used for changing information stored in a cell transistor of the FLASH memory. In addition, the FLASH memory having the floating gate includes a plurality of pumping circuits at a peripheral region to generate a high potential difference of more than 10V. The difficulty in fabricating a FLASH memory device is that transistors and interconnections need to formed under the above potential difference to avoid a breakdown. A SONOS-type non-volatile memory device have been studied to avoid this problem. A SONOS-type non-volatile memory device uses an insulating layer having a trap site, e.g. a silicon nitride layer, as a charge storage layer.
FIGS. 1–3 show a non-volatile memory device in a SONOS structure and a method of operating the same in accordance with the prior art.
Referring to FIGS. 1–3, a gate pattern is disposed on a semiconductor substrate 10. The gate pattern comprises a gate insulating layer 20 and a control gate electrode 30, which are sequentially stacked on the semiconductor substrate 10. Source/drain regions 42 and 44 are disposed in the semiconductor substrate 10 on opposite sides of the gate pattern.
The gate insulating layer 20 comprises a lower insulating layer 22, a charge storage layer 24 and an upper insulating layer 26 which are sequentially stacked. Typically, the lower insulating layer 22, the charge storage layer 24 and the upper insulating layer 26 are formed using silicon oxide, silicon nitride, and silicon oxide, respectively.
The semiconductor substrate 10 includes impurities of a first conductivity type (e.g., p-type) and the source/drain regions 42 and 44 include impurities of a second conductivity type (e.g., n-type). In this case, the concentration of impurities of the source/drain regions 42 and 44 are higher than the concentration of impurities of the semiconductor substrate 10.
FIGS. 1 and 2 are cross-sectional views showing an effect of a bias applied during the programming and erasing steps of a non-volatile memory device. For a brief explanation, only a case that the cell transistor is n-type MOSFET will be considered hereinafter. Referring to FIG. 1, as a voltage applied to the control gate electrode 30 increases, an inversion region 54 and a depletion region 52 are formed at a channel region. As a voltage applied to the drain region 44 increases, the inversion region 54 is pinched off from the drain region 44. Thus, the depletion region 52 is interposed between the drain region 44 and the inversion region 54. In addition, the source region 42 is grounded.
Under this condition, a hot carrier injection may occur between the drain region 44 and the inversion region 54. The hot carrier injection is electrons being injected into the charge storage layer 24. The injected electrons may produce a trapping region 60 in the charge storage layer 24. The electric potential of the channel region is affected by whether or not the trapping region 60 exists during a reading. Thus, the hot carrier injection can be used for the programming of a cell transistor.
Referring to FIG. 2, a positive voltage is applied to the drain region 44 and a negative voltage is applied to the control gate electrode 30. The source region 42 and the semiconductor substrate 10 are grounded. Under this condition, the voltage of the drain region 44 creates a depletion region 56 in the semiconductor substrate 10 around the drain region 44.
Under the above voltage condition, hot holes having enough energy to surmount a potential barrier of the lower insulating layer 22 may be formed. The hot holes may combine with electrons of the trapping region 60 and may be used for an erasing process for removing the trapping region 60 which is formed in the charge storage layer 24. However, the trapping region 60 may not be sufficiently removed by the erasing process and a residual trapping region 62 may be formed in place of the trapping region 60.
Referring to FIG. 3, the trapping region 60 offsets a voltage applied to the control gate electrode 30 during a subsequent programming process. Thus, if the same voltage is applied to a subsequent programming, an abnormal trapping region 64, which is wider than the trapping region 60, is formed in the charge storage layer 60. The abnormal trapping region 64 results in the residual trapping region 62 remaining after the erasing as explained in FIG. 2. The residual trapping region 62 decreases the on-current of a cell transistor, and thereby gives rise to misjudgment on stored information.
FIG. 4 is a graph showing degradation of the nonvolatile memory device of FIGS. 1–3 during the programming and erasing.
Referring to FIG. 4, when the cell transistor is programmed, electrons are injected into the trapping region 60 of the charge storage layer 24. Thus, the reading current of a cell transistor is measured less than a reference current Iref at the reference voltage Vref (4). In addition, when the cell transistor is normally programmed, the trapping region 60 is removed. Therefore, reading current of the cell transistor is measured more than Iref at Vref (1). However, the residual and abnormal trapping regions 62 and 64 of the FIGS. 2 and 3, which result from an incomplete erasing, cause a problem that a threshold voltage Vth of the cell transistor is increased when the Vth is measured after the erasing (2 and 3). In addition, repetition of the programming and erasing give rise to excessive shift of the threshold voltage, so that the reading current of the erased cell transistor may be less than Iref at Vref (3). An insufficient current may cause a wrong reading of the stored data, rendering the semiconductor device defective.
Therefore, there is need for non-volatile memory devices that decrease the operation voltages during the programming and erasing processes of the non-volatile memory device.